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library verilog; use verilog.vl_types.all; entity obufds_blvds_25 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; ob

library verilog; use verilog.vl_types.all; entity nor2 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i0

library verilog; use verilog.vl_types.all; entity bufgp_f is port( o : out vl_logic; i : in vl_logic ); end bufgp_f;

library verilog; use verilog.vl_types.all; entity obuf_lvcmos18_f_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobuf_lvttl_s_2 is port( o : out vl_logic; io : inout vl_logic; i : in vl

library verilog; use verilog.vl_types.all; entity icap_virtex2 is generic( cds_action : string := "ignore" ); port( busy : out vl_logic; o

library verilog; use verilog.vl_types.all; entity bufgs is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity startup_virtex2 is generic( cds_action : string := "ignore" ); port( clk : in vl_logic; gsr

library verilog; use verilog.vl_types.all; entity lut1_l is generic( init : integer := 0 ); port( lo : out vl_logic; i0 : in

library verilog; use verilog.vl_types.all; entity muxf8_l is generic( cds_action : string := "ignore" ); port( lo : out vl_logic; i0