代码搜索结果
找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_sstl3_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor4b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_hstl_iii is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_flag is
generic(
cds_action : string := "ignore"
);
port(
i : in vl_logic
);
end c_flag;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x1s_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clkdlle is
generic(
clkdv_divide : real := 2.000000;
duty_cycle_correction: string := "TRUE";
factory_jf : int
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity srlc16_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity capture_virtex2 is
generic(
cds_action : string := "ignore"
);
port(
cap : in vl_logic;
clk