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library verilog; use verilog.vl_types.all; entity obufdn_f is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ofd_f is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q :

library verilog; use verilog.vl_types.all; entity obuf_s is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuf_hstl_iii_dci is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_hstl_i is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ibufg_lvpecl is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos25_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity ibuf_sstl3_ii_dci is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity rom128x1 is generic( cds_action : string := "ignore"; init : integer := 0 ); port( o

library verilog; use verilog.vl_types.all; entity ramb4_s8_s16 is generic( cds_action : string := "ignore"; init_00 : integer := 0; init_01 : integer