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library verilog; use verilog.vl_types.all; entity sfifo is port( clk : in vl_logic; wen : in vl_logic; wptr : in vl_logic_vec

library verilog; use verilog.vl_types.all; entity mul is port( clk : in vl_logic; nrst : in vl_logic; a : in vl_logic_vecto

library verilog; use verilog.vl_types.all; entity ex4_13 is end ex4_13;

library verilog; use verilog.vl_types.all; entity stackc is port( clk : in vl_logic; nrst : in vl_logic; push : in vl_logic;

library verilog; use verilog.vl_types.all; entity top is generic( row : integer := 96; col : integer := 96; rowsize : integer := 7;

library verilog; use verilog.vl_types.all; entity mem96x96x16 is generic( row : integer := 96; col : integer := 96; rowsize : integer := 7;

library verilog; use verilog.vl_types.all; entity ex6_1 is end ex6_1;

library verilog; use verilog.vl_types.all; entity comp4 is port( a1 : in vl_logic_vector(3 downto 0); a2 : in vl_logic_vector(3 downto 0);

library verilog; use verilog.vl_types.all; entity comp is port( a1 : in vl_logic_vector(3 downto 0); a2 : in vl_logic_vector(3 downto 0);

library verilog; use verilog.vl_types.all; entity ex2_2 is end ex2_2;