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library verilog; use verilog.vl_types.all; entity timegrp is generic( cds_action : string := "ignore" ); end timegrp;

library verilog; use verilog.vl_types.all; entity iobufns_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_logi

library verilog; use verilog.vl_types.all; entity iobufndn_f is port( o : out vl_logic; io : inout vl_logic; i : in vl_logi

library verilog; use verilog.vl_types.all; entity iobufs_f_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_log

library verilog; use verilog.vl_types.all; entity obuft_lvcmos15_f_12 is generic( cds_action : string := "ignore" ); port( o : out vl_logic;

library verilog; use verilog.vl_types.all; entity iobuf_lvdci_dv2_18 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity ofd is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q : o

library verilog; use verilog.vl_types.all; entity cy4_30 is generic( cds_action : string := "ignore" ); port( c0 : out vl_logic; c1

library verilog; use verilog.vl_types.all; entity iobufs_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_log

library verilog; use verilog.vl_types.all; entity ibuf_pci66_3 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i