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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_31 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdrs is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos25_f_2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4b3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vcc is
generic(
cds_action : string := "ignore"
);
port(
p : out vl_logic
);
end vcc;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos18_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_iii is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i