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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvttl_s_12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnn is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_lvcmos15 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram64x2s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildxi_1m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_27 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_hstl_i is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo