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Verilog 的代码
verilog.java
/* -*- tab-width: 4 -*-
*
* Electric(tm) VLSI Design System
*
* File: Verilog.java
* Input/output tool: Verilog Netlist output
* Written by Steven M. Rubin, Sun Microsystems.
*
* Copyright (c)
verilog.vim
" Vim syntax file
" Language: Verilog
" Maintainer: Mun Johl
" Last Update: Thu May 3 09:47:51 PDT 2001
" For version 5.x: Clear all syntax items
" For version 6.x: Quit when
verilog.dump
$date
May 4, 2000 18:30:43
$end
$version
VERILOG-XL 3.0.p001
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var par
verilog.dump
$date
Aug 14, 1997 17:28:33
$end
$version
VERILOG-XL 2.5
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var paramete
verilog.dump
$date
Aug 14, 1997 17:28:33
$end
$version
VERILOG-XL 2.5
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var paramete
verilog.dump
$date
Jul 26, 1997 13:37:48
$end
$version
VERILOG-XL 2.3.3
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var parame
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ex2_6 is
end ex2_6;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
end top;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity csa8_4 is
port(
a1 : in vl_logic_vector(3 downto 0);
a2 : in vl_logic_vector(3 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
end top;