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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildxi_1u is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_iii_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvttl_s_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifd_m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_sstl2_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut2_mux4 is
end lut2_mux4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult18x18 is
port(
p : out vl_logic_vector(35 downto 0);
a : in vl_logic_vector(17 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos33_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvdci_33 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand5 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0