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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufd_s is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufs_f_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufe_f_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_ii_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor2b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufds_ldt_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdi_f is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor4b4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0