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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_s_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity xnor3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fmap_puo is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufds_ulvds_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_pci33_3 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity onor2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgp is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i