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找到约 19,564 项符合 Verilog 的代码

_primary.vhd

library verilog; use verilog.vl_types.all; entity obuf_lvcmos33_s_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos18_s_16 is port( o : out vl_logic; io : inout vl_logic; i : in

_primary.vhd

library verilog; use verilog.vl_types.all; entity xorcy is generic( cds_action : string := "ignore" ); port( o : out vl_logic; ci

_primary.vhd

library verilog; use verilog.vl_types.all; entity or4b2 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i0

_primary.vhd

library verilog; use verilog.vl_types.all; entity buft is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

_primary.vhd

library verilog; use verilog.vl_types.all; entity ifd_u is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q :

_primary.vhd

library verilog; use verilog.vl_types.all; entity obufn is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobuf_lvttl_f_16 is port( o : out vl_logic; io : inout vl_logic; i : in v

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos15_s_4 is port( o : out vl_logic; io : inout vl_logic; i : in

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos18_f_8 is port( o : out vl_logic; io : inout vl_logic; i : in