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Verilog 的代码
verilog.v
// generated by newgenasym Wed Oct 29 11:37:46 2008
module dio (a, k);
inout a;
inout k;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Fri Oct 24 13:50:15 2008
module diozener (a, k);
inout a;
inout k;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Thu Oct 23 15:29:46 2008
module trpnp (b, c, e);
inout b;
inout c;
inout e;
initial
begin
end
endmodule