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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_sstl2_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s4_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos15_s_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_agp is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25_s_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_01 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ild_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :