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Verilog 的代码
verilog.jsf
# JOE syntax highlight file for Verilog
# Define colors
=Idle
=Preproc bold blue
=Comment green
=Constant cyan
=Escape bold cyan
=Type bold
=Keyword bold
# Skip whitespace at start of line
:reset I
verilog.jsf.in
# JOE syntax highlight file for Verilog
# Define colors
=Idle
=Preproc bold blue
=Comment green
=Constant cyan
=Escape bold cyan
=Type bold
=Keyword bold
# Skip whitespace at start of line
:reset I
do_verilog
#!/bin/csh
cp ../bitg/$1.imem arm7.imem
cp ../bitg/$1.dmem arm7.dmem
cp ../bitg/$1.dmemr arm7.dmemr
cp ../bitg/$1.regsr arm7.regsr
verilog testbench_arm7.v
echo register comparison
diff arm7.regout ar