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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut3_d is
generic(
init : integer := 0
);
port(
lo : out vl_logic;
o : ou
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofddrtrse is
port(
o : out vl_logic;
c0 : in vl_logic;
c1 : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity srl16e is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_14 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_aurora_1 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_fl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity srl16e_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffxi_m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q