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Verilog 的代码
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:51:03 08/09/2007
// Design Name:
/
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:12:17 08/07/2007
// Design Name:
/
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:55:39 08/09/2007
// Design Name:
/
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:55:40 08/07/2007
// Design Name:
/
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c12
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:41:20 10/02/2007
// Design Name:
/
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c12
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym