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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflxi_1f is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufgds_blvds_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufen is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1d is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_pci33_5 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand2b1 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0