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library verilog; use verilog.vl_types.all; entity ramb16_s1_s18 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : integer

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos18_f_4 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity obuft_lvttl_f_4 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ibuf_hstl_ii is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity bufe is generic( cds_action : string := "ignore" ); port( o : out vl_logic; e

library verilog; use verilog.vl_types.all; entity ofdti_s_24 is generic( cds_action : string := "ignore"; init : integer := 1 ); port( o

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos25_s_12 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos33_s_8 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity iobufnsn is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity iobuf_sstl3_ii_dci is port( o : out vl_logic; io : inout vl_logic; i : in