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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram64x1d_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_iv is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s18 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_07 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_lvcmos2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufen_f is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_sstl3_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut2_l_mux4 is
end lut2_l_mux4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity srlc16e is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q