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Verilog 的代码
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:50:06 09/21/2007
// Design Name:
/
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:12 09/22/2007
// Design Name:
/
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:47:48 09/19/2007
// Design Name:
/
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:44:16 09/22/2007
// Design Name:
/
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:32:48 09/19/2007
// Design Name:
/
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:36:39 09/18/2007
// Design Name:
/