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library verilog; use verilog.vl_types.all; entity iobuf is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic;

library verilog; use verilog.vl_types.all; entity ramb16_s9 is generic( cds_action : string := "ignore"; init : integer := 0; srval : integer :=

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos15_f_8 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity iobufsn_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_lo

library verilog; use verilog.vl_types.all; entity obuft_lvcmos25_s_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_lvcmos15_s_8 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuf_lvcmos25_f_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuf_lvcmos15 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ilflxi_1 is generic( cds_action : string := "ignore"; init : integer := 1 ); port( q

library verilog; use verilog.vl_types.all; entity obuft_f_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i