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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldpe_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_sstl3_i is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_21 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand3b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode1_int is
port(
o : out vl_logic;
i : in vl_logic
);
end decode1_int;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos25_f_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_hstl_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdce_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufds_lvdsext_33 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i