代码搜索:Vector
找到约 10,000 项符合「Vector」的源代码
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vhd acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
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vhd viterbi_block_pkg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE viterbi_block_pkg IS
TYPE vector_of_std_logic_vector4 IS ARRAY (NATURAL RANGE ) OF std_logic_vector(3 DOWNTO 0);
TYP
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cpp vec_long.cpp
#include
#include
NTL_START_IMPL
static inline
void BlockConstruct(long *, long) { }
static inline
void BlockDestroy(long *, long) { }
NTL_vector_impl
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cpp vec_double.cpp
#include
#include
NTL_START_IMPL
static inline
void BlockConstruct(double *, double) { }
static inline
void BlockDestroy(double *, double) { }
NTL_v
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txt 8bit采样sine波形发生器.txt
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--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is st
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txt 测试向量(test bench)和波形发生器:verilog hdl 程序举例---8bit采样sine波形发生器.txt
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--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is st
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txt 测试向量(test bench)和波形产生:vhdl实例---8bit采样sine波形发生器.txt
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--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is st
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vhd 8bit采样sine波形发生器_vhdl.vhd
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--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is st
www.eeworm.com/read/151251/12226141
vhd 8bit采样sine波形发生器_verilog.vhd
----------------------------------------------------------------------------------
--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is st
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txt 要读的.txt
----------------------------------------------------------------------------------
--
-- "采用ROM结构的8bit采样 sine波形发生器"
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is