代码搜索:Variable

找到约 10,000 项符合「Variable」的源代码

代码结果 10,000
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cpp pointer.cpp

// pointer.cpp -- our first pointer variable #include int main() { using namespace std; int updates = 6; // declare a variable int * p_updates; // declare po
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cpp twofile1.cpp

// twofile1.cpp -- variables with external and internal linkage #include // to be compiled with two file2.cpp int tom = 3; // external variable definition int dick = 30;
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h codegen.h

#ifndef _CODEGEN_H_ #define _CODEGEN_H_ void GenLabel(char lab[LABEL_SIZE]); void StackSegmentBegin(void); void StackSegmentEnd(void); void CodeSegmentBegin(void); void CodeSegmentEnd(void);
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txt rfc1928.txt

组织:中国互动出版网(http://www.china-pub.com/) RFC文档中文翻译计划(http://www.china- pub.com/compters/emook/aboutemook.htm) E-mail:ouyang@china-pub.com 译者:Radeon(Radeon bise@cmmail.com) 译文发布时间:2001-6-18 版权:本
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c three_hi.c

#include void three_hellos(void) { int counter; // Variable for (counter = 1; counter
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txt rfc1928.txt

组织:中国互动出版网(http://www.china-pub.com/) RFC文档中文翻译计划(http://www.china- pub.com/compters/emook/aboutemook.htm) E-mail:ouyang@china-pub.com 译者:Radeon(Radeon bise@cmmail.com) 译文发布时间:2001-6-18 版权:本
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vhd 66_fir.vhd

Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.SIGNED_ARITH.all; use work.coeffs.all; entity fir is port(clk,reset: in std_logic; sample: in signed (
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vhd 62_gcd.vhd

--**VHDL************************************************************* -- -- SRC-MODULE : GCD -- NAME : gcd.vhdl -- VERSION : 1.0 -- -- PURPOSE : Architecture of GCD benchmark -- --
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vhd 27_test_16.vhd

-- Page : 285,286 --Objective : Blocks and 'EVENT vs.'STABLE --Filename : test_16 --Author : Joseph Pick entity Test_16 is end Test_16; architecture Behave_1 o
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vhd 13_shl.vhd

function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is variable v1: MVL7_VECTOR (v2'high downto v2'low); variable shift_val: MVL7_VECTOR (v1'high downto v1'low);