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[COREGEN.VHDL Component Instantiation.tenths] type=template text000=" " text001=" " text002="-- The following code must appear in the VHDL architecture header:" text003=" " text004="component tenths"

[COREGEN.VHDL Component Instantiation.tenths] type=template text000=" " text001=" " text002="-- The following code must appear in the VHDL architecture header:" text003=" " text004="component tenths"

[COREGEN.VHDL Component Instantiation.dpram_core] type=template text000=" " text001=" " text002="-- The following code must appear in the VHDL architecture header:" text003=" " text004="componen

$ Start of Compile #Fri Jun 30 17:00:38 2000 Synplicity VHDL Compiler, version 6.0.0, built May 19 2000 Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved VHDL syntax check successf

Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3.03i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All

-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT.vhd -- VHDL code created by Xilinx's StateCAD 5.03 -- Sat Oct 26 10:39:04 2002 -- This VHDL code (for use with IEEE compliant tools) was generate

-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT.vhd -- VHDL code created by Xilinx's StateCAD 5.03 -- Sat Oct 26 10:39:04 2002 -- This VHDL code (for use with IEEE compliant tools) was generate

$ Start of Compile #Fri Jun 30 17:00:38 2000 Synplicity VHDL Compiler, version 6.0.0, built May 19 2000 Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved VHDL syntax check successf

-------------------------------------------------------------------------------- -- -- Controller Counter Benchmark -- Simulation Vectors -- -- Model Source: Chip Level modelling with VHDL by Ji

-------------------------------------------------------------------------------- -- -- Controller Counter Benchmark -- Simulation Vectors -- -- Model Source: Chip Level modelling with VHDL by Ji