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VHDL 的代码
lock_tw.vhw
-- E:\VHDL\WAITPAST\QIANGDAQI4REN
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Mar 24 14:41:25 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- you
s59_tw.vhw
-- E:\VHDL\WAITPAST\DIG_CLK
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 18 11:36:41 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
m59.vhw
-- E:\VHDL\WAITPAST\DIG_CLK
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 18 11:26:00 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
ch_tw.vhw
-- E:\VHDL\WAITPAST\DIG_CLK
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 18 11:01:14 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
vga_system.map.smsg
Warning (10036): Verilog HDL or VHDL warning at freedev_vga.v(158): object "vga_enable" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at freedev_vga.v(159): object "mem
uart16750.map.smsg
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(226): object "iFCR" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(234): object "iIER_ER
wavetb.do
# Rev: 2.1 24Jan05 TFB - Production
if {$lang == "vhdl"} {
quietly set test_top "tb_vhdl"
} else {
quietly set test_top "tb_vlog"
}
onerror {resume}
quietly WaveActivateNextPane {} 0
a
wavetb.do
# Rev: 2.1 24Jan05 TFB - Production
if {$lang == "vhdl"} {
quietly set test_top "tb_vhdl"
} else {
quietly set test_top "tb_vlog"
}
onerror {resume}
quietly WaveActivateNextPane {} 0
a
wavetb.do
# Rev: 2.1 24Jan05 TFB - Production
if {$lang == "vhdl"} {
quietly set test_top "tb_vhdl"
} else {
quietly set test_top "tb_vlog"
}
onerror {resume}
quietly WaveActivateNextPane {} 0
a
wavetb.do
# Rev: 2.1 24Jan05 TFB - Production
if {$lang == "vhdl"} {
quietly set test_top "tb_vhdl"
} else {
quietly set test_top "tb_vlog"
}
onerror {resume}
quietly WaveActivateNextPane {} 0
a