代码搜索结果

[Library] others = $MODEL_TECH/../modelsim.ini ; Altera specific primitive library mappings work = modelsim_work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1

[Library] others = $MODEL_TECH/../modelsim.ini ; Altera specific primitive library mappings work = modelsim_work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1

[Library] others = $MODEL_TECH/../modelsim.ini ; Altera specific primitive library mappings work = modelsim_work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1

# # ModelSim simulation script # # # project color_conv. # vlib work # Compile vcom -93 -work work ..\\..\\rtl\\vhdl\\ccfactors_pkg.vhd vcom -93 -work work ..\\..\\rtl\\vhdl\\colorconv.vhd vcom -9

[Library] others = $MODEL_TECH/../modelsim.ini ; Altera specific primitive library mappings work = modelsim_work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1

V1 7 FL F:/lqj/1/BulkIn/FPGA/Top.vhdl 2006/11/15.10:40:38 FL F:/lqj/1/FPGA/FPGA/Top.vhdl 2006/10/22.17:59:24 FL E:/study/software/FPGA/FPGA+USB/BulkIn/FPGA/Top.vhdl 2007/07/17.21:24:02 EN work/TOP

V1 7 FL F:/lqj/1/BulkIn/FPGA/Top.vhdl 2006/11/15.10:40:38 FL F:/lqj/1/FPGA/FPGA/Top.vhdl 2006/10/22.17:59:24 FL E:/study/software/FPGA/FPGA+USB/BulkIn/FPGA/Top.vhdl 2007/07/17.21:24:02 EN work/TOP

-------------------------------------------------------------------------- -- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS -- Developed on Nov 1, 1991 by : -- I

-------------------------------------------------------------------------- -- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS -- Developed on Nov 1, 1991 by : -- I

---------------------------------------------------------------------------- -- -- -- Elliptical Wave Filter Benchmark -- -- -- VHDL Benchmark author: D. Sreenivasa Rao --