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-- E:\VHDL\TIMER\KEYDETC_TB.VHD -- VHDL Test Bench created by -- Visual Software Solution's HDL Bencher 1.02 -- Product info/updates: www.testbench.com -- Support: support@testbench.com -- Sales:

NO_OUTPUT_BEGIN This first release of VHDL script file is limited to Simple VHDL Entity Declaration. Clerbois Michel 01/10/96 NO_OUTPUT_END SCRIPT_NOREPEAT_HEADER_BEGIN TYPE STATES is ([NO_RETUR

-- E:\VHDL\PAST\PINGCHE -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Thu Mar 22 18:19:21 2007 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

[Library] others = $MODEL_TECH/../modelsim.ini apa = $MODEL_TECH/../actel/vhdl/apa syncad_lib = C:\Libero\Designer/lib/actel/syncad_lib [vcom] VHDL93 = 1

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[CPU.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 16:07:45 On 2010-

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[Sheet1.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 17:30:38 On 20

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[Sheet1.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 16:52:21 On 20

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[CPU.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 16:07:45 On 2010-

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[Sheet1.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 17:30:38 On 20

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[Sheet1.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 16:52:21 On 20