代码搜索结果

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ctr.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_dec.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_rom.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_alu.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

m255 K3 13 cModel Technology dC:\Dokumente und Einstellungen\yi.luo\Desktop\VHDL\counter\sim Ebcd_2_7seg Z0 w1195056317 Z1 DP ieee numeric_std =NSdli^?T5OD8;4F

{C:/Dokumente und Einstellungen/yi.luo/Desktop/VHDL/watch/src_exercise/design/stop_watch.vhd} {1 {vcom -work work -2002 -explicit {C:/Dokumente und Einstellungen/yi.luo/Desktop/VHDL/watch/src_exercise

D:/VHDL/dds_sin_std1/db/dds_sin.quartus_db dds_sin

D:/VHDL/dds_sin_std1/db/dds_sin.quartus_db dds_sin

{E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd} Model Technology ModelSim SE vcom 6.0 Compiler 2004.08

{E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd} Model Technology ModelSim SE vcom 6.0 Compiler 2004.08