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hdpdeps.ref
V3 3
FL F:/vhdl/fifos/fifo_exp1/fifo_exp1.vhd 2007/12/05.13:07:20 J.33
EN work/fifo89 1197101637 FL F:/vhdl/fifos/fifo_exp1/fifo_exp1.vhd \
PB ieee/std_logic_1164 1173395717 PB ieee/std_logic
netlist.lst
F:\vhdl\fifos\fifo_exp1\fifo89.ngc 1197101644
OK
文件列表.txt
文件列表:
FFT变换的IP核的源代码 VHDL~
...........................\FFT的VHDL源代码
...........................\...............\and_gates.vhd
...........................\...............\baseinde
chipio.xst
set -tmpdir temp
set -xsthdpdir temp
run
-ifn chipIO.prj
-ifmt VHDL
-ofn chipIO
-ofmt NGC
-p xc2s100-6tq144
-ent chipIO
-iobuf YES
chipio.xst
set -tmpdir temp
set -xsthdpdir temp
run
-ifn chipIO.prj
-ifmt VHDL
-ofn chipIO
-ofmt NGC
-p xc2s100-6tq144
-ent chipIO
-iobuf YES
function_generator.jid
. top top.vhd d:\张清明\vhdl程序\function_generator\top.vhd
cancommunication.prj
vhdl work "can2.vhd"
communication.prj
vhdl work "communication.vhd"
finish.prj
vhdl work "can2.vhd"
vhdl work "speed.vhd"
vhdl work "SignalFlash.vhd"
vhdl work "Finish.vhf"
syn_ram.inc
analyze -format vhdl i8051_lib.vhd
analyze -format vhdl i8051_ram.vhd
vhdlout_architecture_name = "SYN"
vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.