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100vhdl+
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distribu
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity tb_decoder is
end tb_decoder;
architecture tb of tb_decoder is
component decoder
port(keypad:in std_logic
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
ENTITY display IS
PORT(reset : IN bit; -- Global reset
clk : IN bit; -- Global clock
en : IN boolean;
unit0 : OUT bit_vector(6 DOWN
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : TESTBENCH
-- NAME : display_stim.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Testbench for display
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
library dsp_lib;
use dsp_lib.delay_macro.all;
use dsp_lib.logic_pack.all;
use dsp_lib.const_pack.all;
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