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100vhdl+
--这是子类型和部件声明的包
--用于区分向量类型的不同宽度
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
PACKAGE pkg_types IS
SUBTYPE bit1 IS std_ulogic;
SUBTYPE bit
100vhdl+
--wss为一个组装程序，把mem_string,mem_sequence,co_processor
--和top controller组装为一个系统
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
--USE ieee.std_logic_unsigned.ALL;
100vhdl+
--Page :303 304
--Objective :Efficient command decoding
--Filename :test_67b.vhd
--Author :Joseph Pick
entity Test_67b is
end Test_67b;
architecture Behave_1
100vhdl+
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
100vhdl+
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
use work.types.all;
architecture BENCH of test_prefetch is
component prefetch
PORT(
BR
100vhdl+
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : PREFETCH
-- NAME : prefetch.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Architecture of PREFETCH b