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找到约 10,970 项符合 VHDL 的代码

usb_new_sieinterface_ent.vhdl

---------------------------------------------------------------------------------- ---- File >>> usb_new_siehandler_ent.vhdl ---- Iden >>> 960312-17:09:34 ---- ---- Project: USB Developmen

usb_new_clkrec_rtl.vhdl

-------------------------------------------------------------------------------- ---- File >>> usb_new_clkrec_rtl.vhdl ---- Iden >>> 951017-16:10:26 ---- ---- Project: USB Development ---

usb_new_pck_configuration.vhdl

-------------------------------------------------------------------------------------- ---- File >>> usb_new_pck_configuration.vhdl ---- Iden >>> 981130-10:32:49 ---- ---- Project:

usb_new_upstreamled_rtl.vhdl

-------------------------------------------------------------------------------- ---- File >>> usb_new_upstreamled_rtl.vhdl ---- Iden >>> 980306-10:26:05 ---- ---- Project: USB De

usb_new_timers_sf_ent.vhdl

-------------------------------------------------------------------------------- ---- File >>> usb_new_timers_sf_ent.vhdl ---- Iden >>> 970604-14:16:07 ---- ---- Project: USB Development

usb_new_timers_sf_rtl.vhdl

--------------------------------------------------------------------------------- ---- File >>> usb_new_timers_sf_rtl.vhdl ---- Iden >>> 970604-14:16:12 ---- ---- Project: USB Development

usb_new_sie_ent.vhdl

------------------------------------------------------------------------------------ ---- File >>> usb_new_sie_ent.vhdl ---- Iden >>> 960123-09:12:02 ---- ---- Project: USB Development --

将16进制转化为std_logic.txt

VHDL: Converting a Hexadecimal Value to a Standard Logic Vector This example shows how to convert a hexadecimal value to a std_logic_vector. It is shown in both VHDL '87 (IEEE Std 1076-1987) and

vhdl2vl.txt

VHDL to Verilog RTL transformer In 1.0 version , some functions restricted, as follows: 1: not all support "Generate" statement,totally not support "if .. Generate " 2: Comment in vhdl may have

reg10.log

==================================================== = vvToForm v0.1 VHDL to Verilog RTL transformer = Release: Brier EDA Studio = *** All Rights Reserved By Brier Van **** ======================