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VHDL 的代码
vga_cntl_xst.prj
vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd"
vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/h
decoder_time_post.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -rpw 100 -ar Structure -te DECODER_TIME_POST -xon false -w -log __projnav/ngd2vhdl.log dec_16b20b.nga DECODER_TIME_POST.vhd
-- Input file:
encoder_time_post.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -rpw 100 -ar Structure -te ENCODER_TIME_POST -xon false -w -log __projnav/ngd2vhdl.log enc_16b20b.nga ENCODER_TIME_POST.vhd
-- Input file:
decoder_time_post.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -rpw 100 -ar Structure -te DECODER_TIME_POST -xon false -w -log __projnav/ngd2vhdl.log dec_16b20b.nga DECODER_TIME_POST.vhd
-- Input file:
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
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VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
topdown.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.