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-------------------------------------------------------------------------------- -- -- Controller Counter Benchmark -- Simulation Vectors -- -- Model Source: Chip Level modelling with VHDL by Ji

--*************************************************************************** -- pack.vhdl * -- VHDL BIT_VECTOR Ope

-------------------------------------------------------------------------------- -- -- Controlled Counter Benchmark -- -- Source: "Chip Level Modeling with VHDL" by Jim Armstrong (Prentice-Hall 19

--Page : 282 --Objective : Infinite oscillation in delta time domain --Filename :test_13 --Author :Joseph Pick entity Test_13 is end Test_13; architecture Behave_1 of Test_1

function bit_to_int (in1:bit_vector) return integer is ALIAS v1: BIT_VECTOR(in1'LENGTH-1 DOWNTO 0) IS in1; variable inpv : bit_vector(in1'LENGTH-1 DOWNTO 0 ); variable SUM: integer

--以下是部件声明的包 --部件mem_sequence,mem_string，以及协处理器分别在以下的包pkg_components中进行了说明 --每一个内存块中包括一个局部控制器，该局部控制器管理一个双向端口的RAM --其中26-36行是mem_sequence的 --73-83行是mem_string的 --实际上每一个双端RAM都将其自己封装为真正的RAM部件 LIBR

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.pkg_types.ALL; ENTITY top IS PORT ( clk : IN bit1; reset : IN bit1;