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test_synth_dp2.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-RAM C
ramlib_quartus.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-RAM C
ramlib_sim.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-RAM C
test_sim.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-RAM C
test_sim_dp2.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-RAM C
test_synth.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-RAM C
baud_gen_stx_beh.prj
vhdl isim_temp "baud_gen.vhd"
platgen.opt
-p virtex4 -lang vhdl -st xst
platgen.opt
-p virtex2 -lang vhdl -st xst
platgen.opt
-p virtex4 -lang vhdl -st xst