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VHDL 的代码
decoder_time_post.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -rpw 100 -ar Structure -te DECODER_TIME_POST -xon false -w -log __projnav/ngd2vhdl.log decoder.nga DECODER_TIME_POST.vhd
-- Input file: de
encoder_time_post.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -rpw 100 -ar Structure -te ENCODER_TIME_POST -xon false -w -log __projnav/ngd2vhdl.log encoder.nga ENCODER_TIME_POST.vhd
-- Input file: en
buffer_comp_chrom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp_chrom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
buffer_comp_chrom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
coregen.crp
SETPROJECT d:\vgashow
SET BusFormat = BusFormatAngleBracket
SET XilinxFamily = Spartan2
SET FlowVendor = Foundation_iSE
SET DesignFlow = Vhdl
SET SimulationOutputProducts = Verilog VHDL
SET Lock
buffer_comp_chrom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp_chrom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
wb_tb_pack.txt
The VHDL file wb_tb_pack.vhd is reused from the SPDIF interface project.
Fetch the file spdif_interface/bench/vhdl/wb_tb_pack.vhd.
gen_control_reg.txt
The VHDL file gen_control_reg.vhd is reused from the SPDIF interface project.
Fetch the file spdif_interface/rtl/vhdl/gen_control_reg.vhd.