代码搜索结果

cnt6,count60,counter60.vhd 计数器的图形和VHDL设计

reg4.vhd，reg4_1.vhd,reg8.vhd,add4.gdf,add8.gdf 流水线加法器 mul_8.vhd，mul8.gdf 流水线乘法器 first.vhd,second.vhd 寄存器VHDL优化编码

C:/Documents and Settings/lxf/桌面/基于quartus的学习开发板试验系统（vhdl编程）/4 pwm/pwm/db/pwm.sim.vwf 499992371 500007629 362 15258 0 C:/Documents and Settings/lxf/桌面/基于quartus的学习开发板试验系统（vhdl编程）/4 pwm/pwm/pwm.vwf 0

This directory contains the examples in the appendix of the "HDL compiler for Verilog" and "VHDL Compiler Reference Manual" These examples can be used to check the operation of the Design compiler or

# # Tcl script file for Chapter 7 # # Read in the design (all designs in the hierarchy) # Analyze and elaborate 5 designs in the lowest hierarchy level # read_file -format vhdl [list {./vhdl/syno

/* design_analyzer script file for Chapter 7 */ /* Read in the design (all designs in the hierarchy) */ /* Analyze and elaborate 5 designs in the lowest hierarchy level */ read -format vhdl {"./vhd

/* link TOP design */ read COMPUTE_BLOCK.db read CONVERTOR_CKT.db read -format vhdl TOP.vhd current_design TOP link /* testability analysis */ set_test_hold 1 TEST_MODE set_test_methodology full_scan

read -format vhdl verilog/new/ALARM_BLOCK.vhd read -format vhdl verilog/new/ALARM_SM_2.vhd read -format vhdl verilog/new/CLOCK_GEN.vhd read -format vhdl verilog/new/COMPARATOR.vhd read -format vhdl ve

read -f pla vhdl/CONVERTOR.pla read -f vhdl vhdl/CONVERTOR_CKT.vhd current_design CONVERTOR_CKT link set_scan_configuration -style combinational uniquify compile check_test create_test_patterns -samp

search_path = search_path + {get_unix_variable(SYNOPSYS_DP) + /power_tutorial, get_unix_variable(SYNOPSYS_DP) + /power_tutorial/lib , get_unix_variable(SYNOPSYS_DP) + /power_tutorial/onehot/vhdl, get_