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VHDL 的代码
100vhdl+
-- Page : 328 - 328
--
-- Objective : Solution for Test_158
--
-- File Name : test_159.vhd
--
-- Author : Joseph Pick
--
entity Test_159 is
end Test_159;
architecture Behav
100vhdl+
--Page :294,295
--Objective :Multiple array inputs
--Filename :test_28.vhd
--Author :Joseph Pick
entity Test_28 is
end Test_28 ;
architecture Behave_1 of Tes
100vhdl+
-- Page : 345 -346
--
-- Objective : constancy of for loop bounds
--
-- File Name : test_194.vhd
--
-- Author : Joseph Pick
--
entity Test_194 is
end Test_194;
architecture
100vhdl+
entity Test_18e is
end Test_18e;
architecture Behave_1 of Test_18e is
signal A : BIT := '0';
signal B : BIT := '0';
signal C : BIT := '0';
begin
Gen_Wave:
process
begin
100vhdl+
--Page : 283
--Objective : Deadlock
--Filename : test_13a
--Author : Joseph Pick
entity Test_13a is
end Test_13a;
architecture Behave_1 of Test_13a is
signal A : NATURA
100vhdl+
--Page :308,309
--Objective :Function slices
--Filename :test_105.vhd
--Author :Joseph Pick
entity Test_105 is
end Test_105;
architecture Behave_1 of Test_
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
entity tb_fq_divider is
end tb_fq_divider;
architecture test of tb_fq_divider is
component fq_divider
port(
clk_in
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--