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找到约 10,970 项符合
VHDL 的代码
p2.udo
-- ProjNav VHDL simulation template: p2.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
q_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_img.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
tabla_q.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
huff_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
dct2d.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
wed.zsf
E:/tool_stud/vhdl/count.vwf 999998228 1000076469 1076 78241 0
E:/tool_stud/vhdl/db/count.sim.vwf 0 2499969024 974 2499969024 0
count.vwf 0 1000000000 867 1000000000 0
read.me
1. Directory structure
* .\src VHDL source files of X_DCT virtual components
* .\tb VHDL test bench of X_DCT, test bench configuration
for RTL simulation, and behavioura
readme.txt
请注意:
第94例是SPARC芯片的源描述,在本书的光盘中没有给出其源描述
代码,有关该描述的框架请参考.
如果您需要有关SPARC的详细资料以及完整代码,请与北京理工大学
ASIC研究所联系.
联系方法:
电话:010-68912434
信函:北京理工大学ASIC研究所 刘明业 教授收
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