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100vhdl+
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
--Notice:
--This file has been modified by Wu Qing-ping on Apr 23, 1998.
--Modification: I change a
100vhdl+
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_gcd_disp is
end t
100vhdl+
--
-- SRC-MODULE : GCD_DISP
-- NAME : gcd.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Architecture of GCD benchmark
--
-- LAST UPDATE: Wed May 19 13:03:48 MET DST 1993
--
--**********
100vhdl+
--本描述是将前述各部件组装成一个完整的系统
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity i486_bus_sys is
end i486_bus_sys;
architecture bus_sys_bhv of i486_bus_sys is
component i486_bus
p
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
entity memory_control is
port (
clk,w_rb,ads_b,cs1 : in bit;
rdy_b,we_b,cs_b : out bit := '1');
end memory_control;
archit
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
use work.bit_pack.all;
use std.textio.all;
entity tester is
port ( address,w_data:out bit_vector(31 downto 0);
r_data:in bit_vector(31 dow
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
--library bitlib;
use work.bit_pack.all;
entity static_ram is
generic ( --下面给出的是RAM6116的时间特性值
--在本系统的组装中将被置为43258A-25CMOS RAM