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[Verilog.User Templates] type=folder [VHDL.User Templates] type=folder [ABEL.User Templates] type=folder

电子时钟 EDA 电子时钟 EDA 一、 <mark>VHDL</mark>的发展 硬件描述语言HDL是一种用形式化方法描述数字电路和系统的语言。利用这种语言，数字电路系统的设计可以从上层到下层（从抽象到具体）逐层描述自己的设计思想，用一系列分层次的模块来表示极其复杂的数字系统。然后，利用电子设计自动化（EDA）工具，逐层进行仿真验证，再把其中需要变为实际电路的模块组合，经过自动综合工 ...

文件列表: FFT变换的IP核的源代码 VHDL~ ...........................\FFT的VHDL源代码 ...........................\...............\and_gates.vhd ...........................\...............\baseinde

#!/bin/csh vcom ../vhdl/mc8051_p.vhd vcom ../vhdl/control_mem_.vhd vcom ../vhdl/control_mem_rtl.vhd vcom ../vhdl/control_mem_rtl_cfg.vhd vcom ../vhdl/control_fsm_.vhd vcom ../vhdl/control

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ram.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ctr.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_dec.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_rom.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_alu.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.