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# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# $Id: Makefile,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $ # all : fm # vasy -V nco.vhdl # vasy -V rom.vhdl # vasy -V addacc.vhdl # verilog : # vasy -V -v nco.vhdl # vasy -V -v r

# [20041030] # * initial write # * changing structural # Makefile for this directory all : fm # vasy -V nco.vhdl # vasy -V rom.vhdl # vasy -V addacc.vhdl # verilog : # vasy -V -v nco.

Simulator report for DDS Mon May 28 16:00:06 2007 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. S

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

set process "5" set part "2s200pq208" set tristate_map "TRUE" set opt_auto_mode "TRUE" set opt_best_result "29223.458000" set dont_lock_lcells "auto" set input2output "30.000000" set input2register "2

/* $Id$ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright