代码搜索结果
找到约 10,000 项符合
VHDL 的代码
100vhdl+
entity bit_rtl_adder is
port (
in1 :IN bit_vector;
in2 :IN bit_vector;
cntl : bit;
pout : out bit_vector
);
end bit_rtl_adder;
architecture func of bit_rtl_adder is
b
100vhdl+
HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
100vhdl+
DLSL
1
BIT_RTL_ADDER.VHDLVIEW U2268397.DLS
100vhdl+
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
100vhdl+
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
100vhdl+
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bit_rtl_adder is
port (
in1 : bit_vector;
in2 : bit_vector;
cntl : bit;
pout : out bit_vector
);
end bit_rtl_adder;
100vhdl+
HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
100vhdl+
entity bit_rtl_adder is
port (
in1 : bit_vector;
in2 : bit_vector;
cntl : bit;
pout : out bit_vector
);
end bit_rtl_adder;
architecture func of bit_rtl_adder is
begin