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------------------------------------------------------------------------------------ ---- File >>> usb_new_sie_ent.vhdl ---- Iden >>> 960123-09:12:02 ---- ---- Project: USB Development --

#!/bin/csh vcom ../vhdl/mc8051_p.vhd vcom ../vhdl/control_mem_.vhd vcom ../vhdl/control_mem_rtl.vhd vcom ../vhdl/control_mem_rtl_cfg.vhd vcom ../vhdl/control_fsm_.vhd vcom ../vhdl/control

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

-- ProjNav VHDL simulation template: test2_v.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

-- ProjNav VHDL simulation template: test3_v.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

-- ProjNav VHDL simulation template: test1_v.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

#!/bin/csh vcom ../vhdl/mc8051_p.vhd vcom ../vhdl/control_mem_.vhd vcom ../vhdl/control_mem_rtl.vhd vcom ../vhdl/control_mem_rtl_cfg.vhd vcom ../vhdl/control_fsm_.vhd vcom ../vhdl/control

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

数字频率计VHDL程序 --文件名：plj.vhd。 --功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的 --高4位进行动态显示。小数点表示是千位，即KHz。 library ieee; use ieee.std_logic_1164.all; use iee

Project Informationd:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\downclk.rpt MAX+plus II Compiler Report File Version 10.12 09/21/2001 Compiled: 12/08/2003 13:16:03 Copyright (C) 1988-2001