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-- Author : yzf -- Created On: Thu Dec 21 09:46:16 1995 -- Testbench for comp.comp architecture BENCH of test_comp is component comp PORT( A: IN SHORT; B: IN SHORT; IN_READY:

-- Author : yzf -- Created On: Thu Dec 21 09:46:16 1995 -- Testbench for comp.comp library STD; library WORK; --library comp; use STD.STANDARD.ALL; --use COMP.TYPES.ALL; use WORK.TYPES.

--**VHDL************************************************************* -- -- SRC-MODULE : COMP -- NAME : comp.vhdl -- VERSION : 1.0 -- -- PURPOSE : Architecture of COMP benchmark --

-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book

---------------------------------------------------------------------------- -- -- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved. -- -- This source file may be used and distribu

--*************************************************************************** -- VHDL BIT_VECTOR Operations for MVL7 type --

-------------------------------------------------------------------------- -- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS -- Developed on Nov 1, 1991 by : -- I

-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book

--Page :301 --Objective :'TRANSACTION of formal parameters --Filename :test_64a.vhd --Author :Joseph Pick entity Test_64a is end Test_64a; architecture Behav