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---------------------------------------------------------------------------- -- -- -- Elliptical Wave Filter Benchmark -- -- -- VHDL Benchmark author: D. Sreenivasa Rao --

---------------------------------------------------------------------------- -- -- -- Elliptical Wave Filter Benchmark : Test Patterns -- -- -- VHDL Benchmark author: D. Sreenivasa Rao

--*************************************************************************** -- pack.vhdl * -- VHDL BIT_VECTOR Ope

--test xilinx cell_lib --use work.types.all; entity E is end E; architecture test_add of E is begin t_add8:block signal a0 : bit := '1'; signal a1 : bit:= '0'; signal a2 : bit:=

---------------------------------------------------- -- The vhdl description for Xilinx Library (4000) -- -- Category: Self-Defined Types and Functions -- -- Yan.Zongfu -- 1995.10.18 ----------------

--**VHDL************************************************************* -- -- SRC-MODULE : TESTBENCH -- NAME : gcd_stim.vhdl -- VERSION : 1.0 -- -- PURPOSE : Testbench for GCD Benchmar

--**VHDL************************************************************* -- -- SRC-MODULE : GCD -- NAME : gcd.vhdl -- VERSION : 1.0 -- -- PURPOSE : Architecture of GCD benchmark -- --