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hdpdeps.ref
V1 8
FL d:/fpga/仿真/divider/compact_divider.vhdl 2006/05/29.11:39:19
FL D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl 2006/05/29.11:39:19
EN work/COMPACT_DIVIDER FL D:/FPGA/仿真/Divider_定点除法器/compact_
hb_cmds
-proj d:\fpga\仿真\divider
-t t_divider.tbw
-source devider.vhdl
-entity devider
-ipcport 1038
q_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_img.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
tabla_q.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
huff_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
dct2d.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
dds.fld
F:/Projects/VHDL/DDS/db/DDS.quartus_db
DDS
compile_all.do
-- ===== ============================= =====
-- ===== Compilation Script for xfft16 =====
-- ===== ============================= =====
--
vcom -87 -work work ./vhdl/radd16.vhd
vcom -87 -work work