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reg4.vhd，reg4_1.vhd,reg8.vhd,add4.gdf,add8.gdf 流水线加法器 mul_8.vhd，mul8.gdf 流水线乘法器 first.vhd,second.vhd 寄存器VHDL优化编码

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

m255 cModel Technology dD:\quartus_30\quartus\tpi\mgc_oem Ecarry_sum DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2 d. FQuartusIIVersion3.0($MODEL_TECH/../altera/Vhdl/src/sgate/sgate.vhd) l0 L865 VKlCX

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Xilinx CORE Generator 6.1.03i # User = compaq Initializing default project... Loading plug-ins... All runtime messages will be recorded in C:\DMATEK_BOOK\BOOK1\STEP_MOTOR_DEGREE_FORWARD_REVERSE_

vhdl work CLK_SET.VHD vhdl work COUNT_0_9.VHD vhdl work COUNT_0_5.VHD vhdl work CLOCK_PACK.vhd vhdl work COUNT_00_59.VHD vhdl work COUNT_00_23.VHD vhdl work DECODER.vhd vhdl work SEGMENT_SCAN_C

# VHDL : PDCL (jhdparse) __projnav/DECODER_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/CLK_SET_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/COUNT_00_23_jhdparse_tcl.rsp # VHDL : P

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth