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VHDL 的代码
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_CONST1 is
-----------------------------------------------------------
generic
(
NU
100vhdl+
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
---------------------------------------------------------
100vhdl+
-------------------------------------------------------HS
-- types and mvl_functions are moved in l2901_lib
-- so that they are not needed to complie every time
-- modified by hanshu,June 4,1
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity tb_alarm_clock is
end tb_alarm_clock;
architecture test of tb_alarm_clock is
component alarm_clock
port(ke