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m255 cModel Technology dD:\quartus_30\quartus\tpi\mgc_oem Elpm_abs DP work lpm_components IGQ_FJj7MiDol1Sb7:UPo1 DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2 DP ieee std_logic_signed

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

EP1K30的GWADDA板A/B口基于DDS的正弦波移相信号发生器 1、打开GW48PK2系统的电源， 注意打开系统的+/-12V电源开关（在系统左上侧）， 2、将GW48系统左下角的拨码开关的“4”向下拨，其余向上。 3、用QuartusII下载2中的DDS_VHDL.SOF，到EP1K30-144中；

Project Information d:\vhdl_ex\moore2.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 11/15/2003 12:40:55 Copyright (C) 1988-2002 Al

read -format vhdl {"config_mietec.vhd"} read -format vhdl {"sparcv8.vhd"} read -format vhdl {"iface.vhd"} read -format vhdl {"macro.vhd"} analyze -format vhdl {"ramlib.vhd"} update_lib

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib