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topclock.prj
vhdl work jhgjgh.vhdl
vhdl work second.vhdl
vhdl work minute.vhdl
vhdl work hour1.vhdl
vhdl work yima.vhdl
vhdl work alm.vhdl
vhdl work main.vhdl
top.prj
vhdl work free_change.vhdl
vhdl work freq_change.vhdl
vhdl work control_unite.vhdl
vhdl work gate.vhdl
vhdl work counter10.vhdl
vhdl work counter.vhdl
vhdl work data_lock.vhdl
vhdl work bcd2seg
clock.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
mux4x1_mixed.syn
JDF B
// Created by Version 2.0
PROJECT Simple 4x1 MUX - Mixed Sch/VHDL Design
DESIGN mux4x1_mixed Normal
DEVKIT ispLSI5256VE-165LT128
ENTRY Schematic/VHDL
STIMULUS mux4x1.abv
MODULE mux4x1.sc
clock.qsf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
hdllib.ref
EN lcd NULL D:/work/vhdl/PBLCD/LCD.VHD sub00/vhpl02 1174189186
AR pblcd behavioral D:/work/vhdl/PBLCD/PBLCD.vhd sub00/vhpl05 1174189189
EN pblcd NULL D:/work/vhdl/PBLCD/PBLCD.vhd sub00/vhpl04 117418
pblcd.lfp
# begin LFP file D:\work\vhdl\PBLCD\PBLCD.lfp
designfile PBLCD.vhd
parttype xc3s200-4-ft256
bus_delimiter -1;
set_busdelim_onsave 1;
motorcombustion.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}