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说明.txt
这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com
dpram2.prj
vhdl work dpram2.vhd
test.udo
-- ProjNav VHDL simulation template: test.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
e10281_obf.vhd
---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool
e10281_bm.vhd
---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool
e10281_ts.vhd
---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool
e10281_sm.vhd
---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool
e10281_ed.vhd
---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool
ch10.03.htm
10.3 Syntax and Semantics of VHDL
ch10.htm
ASICs CHAPTER 10: VHDL